1. Field of the Invention
The present invention relates to interrupt controllers implemented in processors, and more particularly, to interrupt controllers having interrupts that may be masked by software.
2. History of the Prior Art
In a processor, interrupts enable the transfer of control between one software routine and another. An interrupt may be requested by an interrupt request signal as s erred by some internal or external device ( i.e., timer, I/O peripheral ) and received by a Central Processing Unit (CPU). The CPU will typically respond to the interrupt request by temporarily suspending the execution of whatever routine it is running at that time and executing an interrupt service routine. After the interrupt service routine has been executed, the CPU will then resume execution of the former software routine at the point of interruption.
From the foregoing, it can be seen that the use of interrupts allows the CPU to coordinate its activities with those of other devices in a way that eliminates the need for a CPU to waste time polling devices. Also, interrupts are useful in many applications where the processing of certain routines must be accurately timed relative to external events.
Processors generally provide the capability of disabling interrupts by software. Interrupts may be selectively disabled by the CPU by a "masking" technique. This is usually accomplished by the use of an interrupt-enable flip-flop with each interrupt request line. When the flip-flop is set to 1 by software, the flip-flop allows subsequent assertions of the associated interrupt request line to be recognized by the CPU. When the flip-flop is cleared by software, the interrupt request is "masked" and subsequent assertions are not recognized by the CPU.
Some processors, such as those belonging to the Advanced Micro Devices 8051 microcontroller family, provide the capability of masking any number of its interrupts at any time. The capability of masking all interrupts may be useful, for example, in avoiding the interruption of critical software routines, or allowing the CPU to ignore a request from a device until the CPU is ready to service it. There may be times, however, when a non-maskable interrupt may be needed. One such time is when an 8051 microcontroller is in its idle mode.
The idle mode of the 8051 microcontroller offers a means of reducing power consumption by gating off the internal clock signal to its CPU. In its standard configuration, the 8051 microcontroller allows the termination of its idle mode by either a hardware reset or the activation of any enabled interrupt. In some configurations of the 8051 microcontroller, however, the hardware reset mechanism is not available. Even if the hardware reset mechanism is available, it is often undesirable as a means of leaving the idle mode because it re-initializes the computer, thereby losing much of the work done up to that point. Therefore, it is often desirable, if not necessary, to leave at least one interrupt unmasked when the 8051 microcontroller enters idle mode, thereby allowing the microcontroller to exit idle mode by the assertion of an interrupt request.
Those skilled in the art have heretofore encountered a problem in providing for an unmasked interrupt upon the entry into a state such as the idle mode of the 8051 microcontroller. It is known that software is not a reliable method of providing for such an unmasked interrupt. Due to the complexity of modern software, it is difficult for a programmer to account for all possible routes by which the computer could enter into a state such as the idle mode. Also, the microprocessor may enter into such a state inadvertently due to software error or mis-executions in software caused by external noises. On the other hand, providing a permanently non-maskable interrupt is not a desirable method because of the need to mask all interrupts at certain times, as discussed above.
Based on the foregoing, it should be perceived that it may be beneficial for a processor to provide the capability of having all interrupts masked. The processor may enter certain states, however, which it may only exit via an interrupt. If all interrupts have been masked upon entry into such a state, the computer will be caught in a "fatal embrace", that is it will not have a way to exit that state. Although a number of steps have been taken heretofore to deal with this problem, there has yet to have been developed an apparatus or method for an interrupt controller that is extremely effective in coping with it. Accordingly, it should be perceived that it is a shortcoming and deficiency of the prior art that such an apparatus or method has not yet been developed.